The present invention relates generally to communications controllers and more particularly to a communications controller for use in operably coupling a plurality of input/output (I/O) devices to a host central processing unit (CPU).
Data processing systems typically include a CPU, a main memory and one or more I/O devices (commonly referred to as peripheral devices). The I/O devices are usually connected to the CPU through adapters which convert the parallel data received from the CPU into serial data for transmission to the proper I/O device and the serial data received from the I/O devices to parallel data for transmission to the CPU. The adapters are often connected to the CPU through an auxiliary processor which performs certain types of data processing that would otherwise be performed by the CPU. As a result, the CPU has more time to access and process data contained in the main memory.
In U.S. Pat. No. 4,075,691, to Davis et al there is described a control unit for connecting a plurality of peripheral devices to a main CPU. The control unit is comprised of three major sections: (1) A direct memory access module (DMA) for communicating with the memory of the CPU; (2) A serial interface adapter module (SIA) for converting parallel data to serial data for transmission to a peripheral device and serial data to parallel data on receiving from a peripheral device; and (3) A programmable controller module (PCM) connected between the DMA and SIA for providing the overall control of message reception and transmission. The PCM comprises a small special-purpose programmable parallel computer. A program (firmwave) stored in a read-only memory of the PCM enables the PCM to handle the different communication disciplines observed by various peripheral devices operable with the control unit.